Using 2D materials on chips without destroying the wiring

2D materials are typically made at temperatures that wreck silicon chips.

Silicon chip manufacturers like Intel and TSMC are constantly outdoing themselves to make ever smaller features, but they are getting closer to the physical limits of silicon.

“We already have very, very high density in silicon-based architectures where silicon performance degrades sharply,” said Ki Seok Kim, a scientist working at the Massachusetts Institute of Technology’s Research Laboratory of Electronics.

One way around this problem is to replace silicon with graphene-like 2D materials that maintain their semiconducting properties even at a single-atom scale. Another way is building 3D chips, which squeeze more transistors into the same area without making transistors smaller. Kim’s team did both, building a 3D chip out of vertically stacked 2D semiconductors.

Coming in hot

Graphene, a single-atom-thin sheet of carbon, is probably the most famous 2D material, but it's not a semiconductor. There are 2D materials that are good semiconductors, though, like molybdenum disulfide or tungsten diselenide. “They offer very stable electrical performance even below one nanometer,” Kim said. Both molybdenum disulphide and tungsten diselenide belong to a group called transition metal dichalcogenides (TMDs).

These materials are usually grown via a process called chemical vapor deposition, where vaporized materials are sprayed over a substrate and form single-atom-thin crystalline structures on its surface. To make decently performing transistors, those TMDs had to be deposited at temperatures reaching 900º Celsius. That was fine if you wanted just one layer of transistors, but it isn’t compatible with normal silicon fabrication techniques.

The chip manufacturing process starts with a round silicon wafer. Transistors are manufactured on those wafers directly and form the bottom layer of a chip in a part of the chip fabrication process called the front end of line. The first layer of metal wiring, or interconnects, is then added on top of the transistor layer; this is called the back end of line.

If you wanted to add a layer of TMD transistors on top of the back end of line to build a 3D stacked chip, you’d need to heat the whole thing to 900° Celsius, which would basically fry the circuitry. Researchers looking into building 3D chips proposed various solutions to this circuitry-frying problem, but none seemed to work particularly well.

The most popular approach was a process called the through-silicon-via (TSV), which was used to manufacture layers of transistors on separate silicon wafers with drilled microscopic holes to connect the upper wafer with the bottom wafer. But the process was very expensive, and aligning the wafers carefully enough to connect nanometer-scale devices was a challenge. An alternative was to transfer transistors grown on a separate wafer, which solved the hole-drilling issue but left the alignment problem.

Scientists also tried to do chemical vapor deposition of TMDs at temperatures below 400° Celsius, which was considered safe for the metal circuits. But at these low temperatures, TMDs formed poly-crystalline materials instead of single-crystal structures, which significantly degraded their electrical performance.

“The goal was to deposit single-crystalline TMD transistors directly on top of the back end of line in temperatures below 400° Celsius,” Kim said. “This is exactly what we have achieved.”

Nanoscale metallurgy

The solution proposed by Kim’s team was inspired by metallurgy. When a molten metal is poured into a mold, it slowly forms what are called nuclei: grains of solid material that merge to create regular crystal patterns that further harden into solid form. Kim and his colleagues noticed that this nucleation process usually started at the edges of the mold. “Nucleating at the edges requires less energy and heat,” Kim said. So the researchers borrowed this concept and used it to create single-crystalline TMD transistors. They called this technique “geometric confinement.”

Just like with standard chip manufacturing, the process started with a silicon wafer, which was then covered with a thin insulator layer of hafnium oxide. On top of that layer, the team added a polymer coating. That polymer layer was then shaped into trenches—rectangular pockets that were then covered with silicon dioxide. Tungsten diselenide vapor was sprayed over this array of trenches at 485° C as part of the chemical vapor deposition process. This is where the magic happened.

Normally, crystallization forms a polycrystalline material. In a nucleation event, a single-crystalline structure is formed, but as the process goes on, a second nucleation site will rapidly form, and then another, until the whole bulk of material becomes crystallized. The crystalline structures formed in each of those nucleation events are separated by grain boundaries, the signature of a polycrystalline material.

Kim’s team fine-tuned the size of the trenches so that the entire trench could be filled with a crystalline structure formed in a single nucleation event. The crystallization in each trench started with a nucleation event at its edge, just as it would in metal molds. The crystalline structure then filled the trench and ran out of available space just before the second nucleation event could happen.

This formed the first single-crystalline 2D semiconducting layer, which was then turned into transistors by depositing platinum source and drain regions topped with the gate and isolated with another layer of hafnium oxide. That completed the first back end of line.

The second layer of transistors was grown directly on top of the first one using the same process, with two differences. The semiconducting TMD was molybdenum disulfide, which could be deposited at 385° C, and the material used for source and drain regions was chromium. “The electrical performance we achieved was excellent, similar to high-temperature grown TMDs. We demonstrated monolithic, vertically stacked CMOS made with single-crystalline TMDs at below 400° C temperature for the first time,” Kim said.

Getting the temperature of TMDs growth down enough to make large-scale manufacturing feasible could be a huge leap toward making 3D stacked CMOS with 2D semiconductors in actual products people can use. Five members of Kim’s team worked at Samsung’s Device Research Center in South Korea, which might make it look like we’re on the verge of getting this technology to market. The problem is that we need at least one more similar leap before we say goodbye to silicon chips.

Doping problem

Currently, we don’t know how to connect TMD semiconductors with other devices. In today’s chips, connections are achieved by doping: injecting the silicon with impurities to increase its conductivity precisely at points where it interfaces with metal wiring. Those injected impurities smooth out the conductivity drop when the signal is moving between semiconductors and highly conductive materials like chromium, copper, or platinum.

At an atomic scale, doping substitutes atoms of a host metal with foreign atoms. But how do you do that when your host material is one atom thin?

There have been attempts to achieve effects somewhat equivalent to doping in 2D molybdenum disulphide, but the process was difficult to control. In Kim’s paper, the team wrote that developing a doping process for TMDs that can be done below 400° Celsius is necessary to build high-performing chips based on 2D semiconductors. The team thinks its technology may help in growing doped TMDs, but so far, we have no way to do so.

Another looming issue is cooling. Getting the heat out of a super densely packed chip is hard enough with a single layer of transistors. Stacking multiple such layers on top of each other should make the issue considerably worse. “A heat sink area is needed in devices like that. This is also something we plan to do in the future—developing a new cooling scheme for such chips,” Kim said.

But Kim argues that these challenges are worth tackling, as he feels 3D stacked chips based on 2D semiconductors will dramatically increase the performance we can get out of the same chip area and significantly lower the power consumption compared to standard CMOS electronics. And all that will be needed for powering future AI systems.

“We will achieve very, very high-density AI chips,” Kim said.

Nature, 2024.  DOI: 10.1038/s41586-024-08236-9