Rapidus fab roadmap examined — first new leading-edge chipmaker in decades has one Hokkaido fab, a 2027 deadline, and 60 potential customers

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Rapidus semiconductor manufacturing plant under construction in Chitose, Hokkaido

Rapidus is bidding Japan's entire return to leading-edge logic on one fab in Chitose, Hokkaido, and the schedule now turns on a 2027 mass-production target for a 2nm process that no high-volume customer has yet committed to.

Since opening the IIM-1 pilot line in April last year, the company has run wafers through Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached its expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike said the same month that more than 60 companies are in talks over 2nm capacity, but not one has yet signed a volume agreement. Given that its entire production base is the single IIM-1 facility, this leaves Rapidus with no diversification and no fallback site if the node doesn’t go ahead as planned.

However, the fab has the hopes of an entire nation pinned on it, and its plans are promising. Here's the breakdown.

Rapidus is currently targeting 2027 for mass production, but the company has given that date without any further qualification, with its business plan simply pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The same plan sets out a capacity ramp from roughly 6,000 wafer starts per month at the outset to around 25,000 within the first year, a fourfold increase that Rapidus is counting on to bring per-wafer costs down.

IIM-1’s siting in Chitose offers the abundant water that wafer cleaning demands, a cool climate that eases cooling loads, and some of Japan's strongest renewable-energy potential across wind, solar, and hydro. Local and prefectural authorities have organized around the project under a “Hokkaido Valley” initiative that aims to build a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.

Rapidus’s 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to learn the node, with roughly 80 later returning to Chitose to transfer and tune the process for production, according to IBM.

The differentiator the company is leaning on is manufacturing flow, with IIM-1 running single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. It’s understood that the 2nm Process Design Kit (PDK) reached early customers in Q1 this year. Still, Rapidus hasn’t yet published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.

The program extends beyond the wafer, with Japan’s New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus providing funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also floated panel-level glass-substrate packaging as part of its longer-term roadmap. Building that back-end capability in Chitose rather than outsourcing it would mirror the integrated approach Intel and Samsung take.

Rapidus’s February funding round closed at ¥267.6 billion, or about $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment, the first made possible by a 2025 revision to Japan's subsidy law permitting government equity in Rapidus, made Tokyo the largest single shareholder, with a golden share giving it veto power over major decisions, including share transfers and technology partnerships.

That round sits on top of a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, taking Rapidus’s combined capital and capital reserves to around ¥425 billion. The shares the state holds are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates, a clause that pairs with the golden share to give Tokyo both upside alignment and a downside lever.

Rapidus’s buildings and equipment are also currently owned by Japan's New Energy and Industrial Technology Development Organization (NEDO) and leased back, with the company previously obligated to buy them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.

Koike said in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10 of them. The names attached to those talks in reporting by TrendForce are IBM and the Canadian RISC-V accelerator startup Tenstorrent, with Fujitsu, a founding investor, separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, the firm led by chip architect Jim Keller and currently being considered for takeover by Qualcomm, agreed back in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center (LSTC) project, with Tenstorrent handling the CPU and Rapidus' AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.

Neither of these amounts to the committed high-volume order that Rapidus needs, and fast. Koike has described interest as growing “like a runaway steam engine,” but interest is not the same as allocation. Rapidus’s cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan’s current mainstream parts, a premium that’ll only narrow with volume.

A second Kumamoto fab broke ground in 2025, and its planned node was upgraded twice, first to 4nm and then to 3nm, with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north. The Kumamoto plants carry far less technical risk and are already shipping; Rapidus carries nearly all of the program's execution risk and none of its proven output.

Even as the 2nm line ramps, Rapidus plans to begin 1.4nm process development in 2026, start construction on a 1.4nm fab in 2027, and reach mass production around 2029. The node leans on the company's research ties: Rapidus joined imec's core partner program in April 2023, giving it access to the Belgian institute's pilot line, and imec's position is that 1.4nm single-patterned layers require High-NA EUV, the 0.55 numerical-aperture tool that resolves the most critical metal layers in one exposure rather than several. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production, according to figures cited by both TrendForce and Nikkei.

Rapidus’ financials highlight how far all this is from being self-sustainable, having posted a ¥375 million loss for fiscal 2025 with total assets of ¥749.5 billion, while still aiming to raise around ¥1 trillion from private investors. The ASEAN+3 Macroeconomic Research Office has been cited as estimating that committed funding still falls short of the roughly ¥5 trillion needed for stable production, dependent on a private investor base that has yet to materialize at scale.

Meanwhile, TSMC moved its N2 node to volume production in late 2025, and Samsung began first-generation SF2 mass production the same year, which puts Rapidus roughly two years behind both on a node that customers can already buy elsewhere with proven yields. There’s also something of an adversarial backdrop developing: TSMC employees were reportedly accused last year of taking 2nm trade secrets said to be destined for Rapidus, an allegation a Japanese government official later characterized as non-critical. The episode has no confirmed bearing on Rapidus’s process, which is built on IBM IP.

Rapidus is targeting operating profitability around fiscal 2030 and an IPO in fiscal 2031, a timeline that assumes the 2027 ramp lands on schedule and that the customers now in talks convert into committed volume. Three milestones will indicate whether those targets are possible: a named customer with a committed volume order, evidence that 2nm yields are tracking toward the levels TSMC and Samsung already run at, and confirmation that the capacity ramp is hitting its 25,000-wafer target.

Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.

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