SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements

SRAM scaling came to a screeching halt with the last round of new process nodes, portending a dark future where on-chip memories would become increasingly expensive. However, contrary to what we've seen in the past, SRAM scaling apparently isn't dead after all. 

TSMC has announced that its N2 process technology (2nm-class) offers substantial improvements in performance, power efficiency, and area (PPA) compared to previous-generation nodes. However, there is one more thing that TSMC hasn't yet publicly discussed: considerably smaller SRAM cells and higher SRAM density (38 Mb/mm^2), which will have an impact on the costs and performance of next-generation CPUs, GPUs, and system-on-chips.  

TSMC's upcoming N2 node will debut with gate-all-around (GAA) nanosheet transistors, promising a significant power reduction and a boost in performance and transistor density. Compared to the N3E fabrication technology, chips built on N2 are expected to reduce power usage by 25% to 30% (at equivalent transistor count and frequency), boost performance by 10% to 15% (with the same transistor count and power), and achieve a 15% increase in transistor density (maintaining the same speed and power). 

But a noteworthy aspect of TSMC's N2 is that this production node also shrinks HD SRAM bit cell size to around 0.0175 µm^2 (enabling SRAM density of 38 Mb/mm^2), down from 0.021 µm^2 in the case of N3 and N5, according to a paper that TSMC will present at the upcoming IEDM conference this December. 

This is a major breakthrough as SRAM has become particularly hard to scale in recent years. For example, TSMC's N3B (1st Generation 3nm-class technology) provided little advantage over N5 (a 5nm-class node) in this regard, while the HD SRAM bit cell size of N3E (2nd Generation 3nm process) is 0.021 µm^2 and offers no advantages in terms of SRAM scaling compared to N5. With N2, TSMC has managed to finally shrink HD SRAM bit cell size and, therefore, increase SRAM density. 

TSMC's GAA nanosheet transistors appear to be the main enabler of smaller HD SRAM bit cell sizes. GAA transistors offer improved electrostatic control over the channel by completely surrounding it with the gate material, which helps reduce leakage and allows transistors to scale down in size while maintaining performance. This enables better scaling of transistor dimensions, which is crucial for reducing the size of individual components like SRAM cells. Also, GAA structures allow for more precise threshold voltage tuning, which is essential for the reliable operation of transistors overall, and SRAM cells in particular, making it possible to further shrink their sizes. 

Modern CPU, GPU, and SoC designs are very SRAM-intensive as these processors rely heavily on SRAM for numerous caches to handle large amounts of data efficiently. Accessing data from memory is both performance-draining and power-intensive, making ample SRAM crucial for optimal performance. Looking ahead, demand for caches and SRAM is set to keep growing, so TSMC's achievement with SRAM cell size represents a very important one. 

Earlier this year, TSMC said that N2's gate-all-around nanosheet transistors were delivering over 90% of their target performance, and yields for 256 Mb (32 MB) SRAM devices were surpassing 80% in certain batches. As of March 2024, the average yield for 256 Mb SRAM had reached approximately 70%, up significantly from around 35% in April 2023. Device performance has also shown steady improvement, with higher frequencies achieved without increasing power consumption.