Silicon is starting to design silicon — how AI is being used in chipmaking, from EDA tools to OpenAI's Jalapeño and beyond

In late August, Architect Labs claimed it had designed a chip that was almost entirely developed by AI, an industry-first achievement. AI is already used to optimize floorplans, placement and routing, verification, and other stages of semiconductor development. Generative AI can assist engineers with RTL code, whereas emerging agentic systems can operate electronic design automation (EDA) tools, analyze results, identify problems, modify designs, and repeat the process with increasingly less human intervention. Meanwhile, human engineers still define and develop architectures and make fundamental design decisions that determine what a chip does and how it works.

This creates a curious feedback loop. Today's AI models run on processors designed by human engineers with growing assistance from AI; those models can then help design more capable processors for the next generation of AI systems. As EDA vendors and semiconductor companies give AI control over progressively larger portions of the design process, the industry is gradually moving from humans using AI tools to design chips toward AI systems participating in the design of the hardware on which their successors will run.

Can machines indeed design machines today? Probably not. But will they be able to do so in the future? That's a big question with important ramifications — and engineers have been pondering it for longer than you might think.

A brief history of AI in chip development

Cadence, Synopsys, and Siemens EDA, all leading developers of EDA software, alongside Ansys — a leading designer of simulation software — rolled out AI-enhanced versions of their tools in the early 2020s, before the generative AI boom took the world by storm.

The first generation of AI-enhanced EDA software primarily used machine learning (ML) and reinforcement learning (RL) to tackle well-defined optimization problems. Given an existing design, a set of constraints, and particular targets, these tools could explore numerous implementation options to optimize placement and routing, and therefore power, performance, and area (PPA), while shrinking development time. Essentially, AI could find a better way to implement a design, but the design itself and its goals were still defined by engineers.

One of the key advantages of these tools was their ability to learn from previous runs and use accumulated data to guide subsequent design-space exploration, something which could reduce the number of iterations needed to meet PPA targets and, in some cases, produce results that would have required considerably more engineering time using conventional methods. Yet the autonomy of these tools is limited, as engineers define constraints, configure flows, run individual tools, analyze their output, and decide what to try next. AI accelerates or optimizes particular stages of chip development, but humans still control the overall design flow. And that's changing with newer generations.

The latest AI-enhanced EDA tools are considerably more ambitious. Generative AI can write or modify RTL and verification code, analyze reports, identify potential points of failure, and even suggest fixes. Meanwhile, emerging agentic systems can operate multiple EDA tools and execute sequences of engineering tasks with very limited human intervention. Such an agent can analyze results, modify a design or its parameters, launch another simulation or implementation run, evaluate the outcome, and repeat the process until it reaches specified targets. As a result, AI is gradually moving from optimizing individual steps inside EDA tools to automating parts of the chip development workflow itself.

From big bang to architectures

In 2023 – 2024, both Cadence and Synopsys announced that hundreds of chip designs have been completed using their AI-enhanced Cadence.ai DSO.ai/VSO.ai/TSO.ai tools. Moreover, leading high-tech companies revealed details about how they used AI to complete their projects. Yet putting Google, Nvidia, OpenAI, and Architect Labs into the same bucket is not right, as they represent different degrees of AI involvement in chip development.

Google, which was among the first high-tech giants to announce the use of AI to develop its AI accelerators, seems to be the least radical. Google's AlphaChip uses reinforcement learning mostly for physical floorplanning: it places circuit blocks and optimizes layouts, but it does not invent the entire design or the architecture itself. Google DeepMind said in 2024 that AlphaChip had been used for the previous three generations of TPUs, meaning Google was well ahead of the general EDA industry with its tools. (The company has not shared AlphaChip's progress in detail since then.)

Nvidia is more interesting because its internal AI systems tend to automate work traditionally performed by hardware engineers. The important distinction is that Nvidia trains specialized models on its own RTL, documentation, and unique accumulated engineering knowledge, something a merchant EDA vendor cannot access. This makes Nvidia an example of a chip designer that turns the engineering data behind its proprietary GPU and, more recently, AI accelerator, CPU, DPU, and network cards into training data for AI. Nonetheless, Nvidia itself draws a clear line between its automation and autonomous chip design.

OpenAI's Jalapeño is probably the strongest real-silicon example we currently have. OpenAI says AI was directly involved in implementation, design-space exploration, verification loops, and arithmetic-circuit optimization, which enabled the company to go from initial design to tapeout in nine months. At Hot Chips, OpenAI disclosed some concrete PPA advantages: Compared with human baselines, AI-assisted designs improved a BF16 multiplier by 56%, an FP4 dot-product block by 21%, and an FP32 accumulator by 10%, while reducing the area of matrix and SIMD units by 10% and 8%, respectively.

OpenAI has not said that AI invented Jalapeño's architecture, so humans have indeed remained responsible for it. But AI was extensively used to turn that architecture into silicon and optimize it ... which brings us to Architect Labs.

Indeed, Architect Labs' Redwood is qualitatively different. Two human architects defined the specification, after which Architect Labs says its AI autonomously generated and verified the logic, generated RTL, verified it, and produced firmware. To top it off, AI also assisted software development, including drivers and kernels. Meanwhile, unlike Google, Nvidia, and OpenAI, the company explicitly describes its system as one that performs machine learning co-design and says it can explore architectures, though without elaboration.

Redwood was 'produced' in under two weeks and runs billion-plus-parameter models, but there is a huge caveat: It has not been taped out. It has never actually been produced as an ASIC; the accelerator runs on an FPGA, and the claimed 3.4X performance-per-watt advantage over Nvidia's Jetson Orin Nano is based on a projected Samsung 8LPP design.

Final words

Just a few years ago, AI in semiconductor development was largely an optimization technology that helped engineers find better ways to implement designs created by humans. Today, it can generate RTL, verify designs, operate EDA tools, and even explore architectural choices, although humans still define what ultimately gets built.

We are therefore considerably closer to machines designing machines, but nowhere near the singularity quite yet. For now, chips are helping design their successors. But they aren't even close to deciding what those successors should be.