Intel reveals 288-core Clearwater Forest Xeon at Hot Chips — 18A process' first outing promises big efficiency and performance gains

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A datrk render of a data center
(Image credit: Shutterstock)

Intel pulled the wraps off its first all-E-core Xeon at Hot Chips on Monday, August 25, in Cupertino, California. Dubbed Clearwater Forest, it's the first Xeon built on the company’s next-gen 18A process.

Scheduled to ship in 2026, the processor packs a punch with 288 efficiency cores and a two-socket ceiling of 576 cores, as well as over 1,152 MB combined last-level cache. On paper, it’s Intel’s next attempt to close the performance-per-watt gap in the data center, and it’s a shot across the bow at AMD’s EPYC line.

Intel Clearwater forest
(Image credit: Intel)

Darkmont cores bring modest IPC gains, massive scale

Architecturally, Clearwater is a spiritual sequel to Intel’s 144-core all-E-core Xeon, Sierra Forest, but with a few notable upgrades. The new Darkmont E-cores offer a wider 3x3 decode engine, deeper out-of-order windows, and enhanced execution ports, resulting in approximately 17% better IPC than the Crestmont generation.

Four cores share 4MB of L2 cache, and the chip doubles L2 bandwidth compared to the Sierra. Multiply that across 288 cores, and you’ve got a throughput monster designed to eat multithreaded web services and AI inference jobs alive.

The choice of process matters just as much as core count. Clearwater is one of the first real-world testbeds for Intel’s 18A node, which pairs RibbonFET transistors with backside power delivery.

This is effectively Intel’s answer to the density and power efficiency questions that have enabled TSMC and AMD to dominate in recent years. By separating power and signal routing, Intel claims higher cell utilization and lower IR drop, features that hyperscalers care about when power bills stretch into megawatts.

A new definition of Xeon?

Compared to AMD’s 128-core Bergamo, Clearwater plays an entirely different game. AMD cores support SMT, AVX-512-class vector units, and higher single-thread performance. In contrast, Intel’s cores don’t chase peak IPC; they chase scale. That means Clearwater might not top benchmarks in HPC or AI training, but in raw thread count and total throughput, Intel says it's well ahead. A two-socket Clearwater box can theoretically support over 1,000 vCPUs per rack, while Intel is claiming 3.5x better perf-per-watt versus its previous Xeons.

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The bigger question is whether customers buy into Intel’s efficiency-first bet. For decades, Xeon has been synonymous with P-cores, but Clearwater is different. It’s a data center processor that doesn’t care about prestige benchmarks, but rather how many workloads it can cram into a rack without blowing the power budget. If Intel’s numbers hold, the firm expects Clearwater Forest to redefine what Xeon is supposed to be, rather than simply being a new iteration.

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Luke James is a freelance writer and journalist.  Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory. 

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