Intel patents 'Software Defined Supercore' — increases single-thread performance and IPC by mimicking ultra-wide execution using multiple cores

Intel has patented a technology it calls 'Software Defined Supercore' (SDC) that enables software to fuse the capabilities of multiple cores to assemble a virtual ultra-wide 'supercore' capable of improving single-thread performance, provided that it has enough parallel work. If the technology works as it is designed to, then Intel's future CPUs could offer faster single-thread performance in select applications that can use SDC. For now, this is just a patent which may or may not become a reality.

Intel's Software Defined Supercore (SDC) technologies combine two or more physical CPU cores to cooperate as a single high-performance virtual core by dividing a single thread's instructions into separate blocks and executing them in parallel. Each core runs a distinct portion of the program, while specialized synchronization and data-transfer instructions ensure that the original program order is preserved, maximizing instructions per clock (IPC) with minimal overhead. This approach is designed to improve single-thread performance without increasing clock speeds or building wide, monolithic cores, which can increase power consumption and/or transistor budgets.

Modern x86 CPU cores can decode 4–6 instructions and then execute 8-9 micro-ops per cycle after the instructions are decoded into micro-ops, which achieves peak IPC performance for such processors. By contrast, Apple's custom Arm-based high-performance cores (e.g., Firestorm, Avalanche, Everest) can decode up to 8 instructions per cycle and then execute over 10 instructions per cycle under ideal conditions. This is why Apple's processors typically offer significantly higher single-threaded performance and lower power consumption compared to Arm counterparts.

While it is technically possible to build an 8-way x86 CPU core (i.e., a superscalar x86 processor that can decode, issue, and retire up to 8 instructions per clock), in practice, it has not been done because of front-end bottlenecks as well as diminishing returns in terms of performance increase amid significant power and area costs. In fact, even modern x86 CPUs can typically hit 2–3-4 sustained IPC on general workloads, depending on software. So, instead of building an 8-way x86 CPU core, Intel's SDC proposes pairing two or more 4-wide units to cooperate as one large core in cases where it makes sense.

On the hardware side, each core in an SDC-enabled system includes a small dedicated hardware module that manages synchronization, register transfers, and memory ordering between paired cores. These modules utilize a reserved memory region — known as the wormhole address space — to coordinate live-in/live-out data and synchronization operations, ensuring that instructions from separate cores retire in the correct program order. The design supports both in-order and out-of-order cores, requiring minimal changes to the existing execution engine, which results in a compact design in terms of die space.

On the software side, the system uses either a JIT compiler, a static compiler, or binary instrumentation to split a single-threaded program into code segments to assign different blocks to different cores. It injects special instructions for flow control, register passing, and sync behavior, enabling the hardware to maintain execution integrity. Support by the operating system is crucial as the OS dynamically decides when to migrate a thread into or out of super-core mode based on runtime conditions to balance performance and core availability.

Intel's patent does not provide exact numerical performance gain estimates, but it implies that in select scenarios, it is realistic to expect the performance of two 'narrow' cores to approach the performance of a 'wide' core.

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